Superjunction device with improved ruggedness

ABSTRACT

An improved superjunction semiconductor device includes a charged balanced pylon in a body region, where a top of the pylon is large to create slight charge imbalance. A MOSgated structure is formed over the top of the pylon and designed to conduct current through the pylon. By increasing a dimension of the top of the pylon, the resulting device is less susceptible to variations in manufacturing tolerances to obtain a good breakdown voltage and improved device ruggedness.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No.10/968,499, filed Oct. 19, 2004, entitled SUPERJUNCTION DEVICE WITHIMPROVED RUGGEDNESS which is based on and claims priority to U.S.Provisional Application Ser. No. 60/513,174, filed Oct. 21, 2003,entitled SUPERJUNCTION DEVICE WITH IMPROVED RUGGEDNESS, the entirecontents of which are incorporated herein by reference.

FIELD OF THE INVENTION

This invention relates to superjunction devices and a process for theirmanufacture, and more specifically to the increase of the ruggedness ofsuperjunction devices, and the increase of the process window tolerancesfor such devices.

BACKGROUND OF THE INVENTION

Superjunction devices possess the advantage of significantly reducedR_(dson) for the same high breakdown voltage (BV) of a conventionalMOSFET. The superjunction is comprised of a multi-layer, for example, asix-layer sequence of implant and epitaxy to form spaced P-columns whichis used to balance the charge in the N type drift region epi whichreceives the columns. The same reticle is used repetitively on the sixlayers to generate the P-column.

The charge balance is critical with a small process window. Exceedingthis window on the P-type side (that is, having an excessive P charge inthe P columns) leads to the BV falling below the spec. Exceeding thiswindow on the N-type side leads to high BV but can lead to ruggednessreduction.

Device ruggedness can be enhanced by structural modifications that forcethe current to flow through the P-column rather than outside it. Suchstructures are shown in copending application Ser. No. 60/417,212, filedOct. 8, 2002 and assigned to the assignee of the present invention, andwhich is incorporated herein by reference. In that case, the top-mostportion only of the P columns had a higher and unbalanced Pconcentration (charge) than the remainder of the columns, which have abalanced concentration against the surrounding N type body. This causedavalanche current at the top of the columns to be diverted from underthe MOSFET source regions (the R_(b)′ region) and toward the axis of thecolumn.

BRIEF DESCRIPTION OF THE INVENTION

The invention proposes a different modification. Instead of using thesame design for all the layers, the topmost layer design is modifiedwith a slightly larger feature (diameter) and thus increased volume andP charge, solely in the active area such that the BV of the active areacells is reduced selectively and also so that the current flows into ortoward the axis of the P column, thus improving the ruggedness. Thelower 5 layers and the termination can then be optimized for maximum BV.The use of the separate upper or 6^(th) layer design will allow therealization of high termination BV, relatively lower active area BV andcurrent flow in the P-column. The conjunction of these 3 factors willimprove the ruggedness and increase the process window tolerance sinceit reduces the dependence of the EAS on the device BV. Note that while asix layer design has been chosen to illustrate the invention, any numberof layers can be used.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-section of a small portion of the active area of asuperjunction device, which employs the present invention.

FIG. 2 is a cross-section of FIG. 1 taken across section line 2-2 inFIG. 1.

FIG. 3 shows the process step of forming an enlarged volume P section atthe top of the P columns in accordance with the invention.

DETAILED DESCRIPTION OF THE INVENTION

Referring to FIGS. 1 to 3, a silicon wafer (sometimes referred to as adie or chip) is formed of an N⁺ wafer 10 which receives a series ofepitaxial layers N₆ to N₁ which are sequentially formed. After theformation of each layer, an implant and diffusion is carried out to formP regions (P₆ to P₁ respectively). In the prior art, the implant anddiffusions are identical in size and concentration and which are chargebalanced to the surrounding charge of layers N₆ to N₁ respectively,which are each of the same concentrations.

Each of P regions P₆ to P₁ are aligned to one another to form acontinuous column or “pylon”.

A MOSgated structure is then formed atop each column, shown in FIG. 1 asP channel regions 20, 21 and 22 which conventionally receive N⁺ sourceregions 24, 25 and 26 respectively. A gate oxide 27 is deposited overthe inversion areas of each of channel regions 20, 21 and 26respectively and a conductive polysilicon gate 28 is formed over each ofgate oxide regions 27. An LTO insulation layer 29 is formed over gates28 and a source electrode 30 is formed over the layer 29 and contactseach of sources 24, 25, 26 and the inner channel of regions 20, 21 and22. Note that the channel regions 20, 21 and 22 may be polygonal cellsor stripes; and columns P₆ to P₁ have corresponding circular or stripeshapes. A drain electrode 40 is attached to the bottom of N⁺ region 10.

In accordance with the invention, the uppermost P regions P₁ have agreater diameter then that of the underlying regions P₂ to P₆, so thatthe top of the columns will have a greater P charge than that of thesurrounding N₁ layer. The top-most column may have an increased diameterof only a few percent over that of the lower columns. By way of example,if the lower column elements P₂ to P₆ have a diameter, after diffusionof 5 microns, the top P region P₁ may have a diameter of 5.1 microns (2%greater) to obtain the benefits of the invention.

FIG. 3 shows the implant and diffusion of the top P region P₁. Thus, thelayer N₁ is deposited atop layer N₂ and its P regions P₂. A mask 50 isthen formed atop layer N₁ with windows 51, 52 aligned with the center ofregion P₂. A boron or other P species implant and diffusion is thencarried out to form the enlarged diameter regions P₁ aligned to the topsof the P columns. However, the window diameter for windows 51 and 52 arelarger than the implant windows in the mask for regions P₂ to P₆,creating the enlarged diameter top region P₁. Alternately, the diffusionprocess is carried out for a longer period of time to form enlargedregions P₁.

While the windows 51 and 52 are circular (FIG. 2), other shapes can beused for windows 51 and 52, such as elongated stripes, rectangles,ovals, or circles with projecting fingers, and the like to produce alarger P volume at the top of each column. In addition, regions P₁ neednot be formed on every column over region P₂. Some column may include aP₁ region that is the same size as region P₂ or other regions in the Pcolumns. These columns may be interspersed throughout the semiconductordevice to obtain particular characteristics for the device.

Further, while the description above contemplates identical diameters(or widths) for P regions P₂ to P₆, they may be continuously tapered orstepped down in diameter from a larger diameter for regions P₂ to asmaller diameter for regions P₆. In addition, a number of upper Pregions may be enlarged to some extent, and be in charge imbalance withthe surrounding N type material. For example, the topmost two or three Pregions may be enlarged in comparison to the lower P regions, and be incharge imbalance with the surrounding N type material.

Although the present invention has been described in relation toparticular embodiments thereof, many other variations and modificationsand other uses will become apparent to those skilled in the art. It ispreferred, therefore, that the present invention be limited not by thespecific disclosure herein.

1. A method for forming a superjunction device on a substrate having afirst conductivity type, the method comprising the steps of: forming aplurality of first layers of semiconductor material over the substrate,the first layers of semiconductor material being of the firstconductivity type; forming a second layer of semiconductor material overthe plurality of first layers, the second layer of semiconductormaterial being of the first conductivity type; diffusing semiconductormaterial of a second conductivity type in a plurality of verticallyaligned regions on each of the first and second layers, the plurality ofregions forming spaced pylons whose widths are narrower than a distancebetween two adjacent pylons, wherein dimensions of the verticallyaligned regions of the second layer are larger than dimensions of thevertically aligned regions of the first layers.
 2. The method of claim1, wherein the first conductivity type is N-type and the secondconductivity type is P-type.
 3. The method of claim 1, wherein thedimensions of the vertically aligned regions of the second layer areapproximately 2% greater than the dimensions of the vertically alignedregions of the first layers;
 4. The method of claim 3, wherein thevertically aligned regions of the second layer are out of charge balancewith a region surrounding the pylon.
 5. The method of claim 3, whereinthe vertically aligned regions of the first layer are in charge balancewith the region surrounding the pylon.
 6. The method of claim 1, whereinthe pylon has a substantially cylindrical shape.
 7. The method of claim1, wherein the superjunction device has improved avalanche capability.8. The method according to claim 1, further comprising the step offorming a MOSgated structure atop the second layer, the MOSgatedstructure having a source contact in a source region, a gate electrodein a channel region positioned above and in contact with a pylon, and amajor electrode on a bottom of the substrate.
 9. A method for forming asuperjunction device having improved avalanche capability, the methodcomprising the steps of: forming a layer of semiconductor material on asubstrate, the substrate and the layer being of N-type conductivity;diffusing semiconductor material of P-type conductivity in a pluralityof vertically aligned regions in the layer, the plurality of regionsforming spaced pylons whose widths are narrower than a distance betweentwo adjacent pylons and length equals that of the width of the layer,wherein dimensions of an area of each pylon farthest from the substrateand constituting a portion of the total area of the pylon, areapproximately 2% greater than dimensions of the rest of the pylon. 10.The method of claim 9, wherein the area of each pylon farthest from thesubstrate and constituting the portion of the total area of the pylon isout of charge balance with a region surrounding the pylon while the restof the pylon is in charge balance with the region surrounding the pylon.11. The method of claim 9, wherein the portion is about 10% to 20%. 12.The method of claim 9, wherein the pylon has a substantially cylindricalshape.
 13. A method for forming a superjunction device, comprising:providing a substrate having one conductivity type; overlaying thesubstrate with a semiconductor material having the same conductivitytype; diffusing a semiconductor material of the other conductivity typeinto the overlying layer; forming another layer over the overlying layerhaving the one conductivity type; diffusing a semiconductor material ofthe other conductivity type into the another layer to form an implanthaving a larger dimension than that of the first implant.
 14. The methodaccording to claim 13, further comprising: forming a MOSgated structureatop the topmost diffusion and having a source and channel region; andforming a source contact over the source region; forming a gateelectrode over the channel region.